1. Technical Field
This invention relates generally to methods of fabricating a semiconductor device, and more particularly, to methods of fabricating a semiconductor device by using an organic compound and fluoride-based buffered solution to perform a wet etching step during the fabrication process.
2. Discussion of the Related Art
Generally, semiconductor devices are being fabricated for the characteristics of high-integration and high-speed in order to satisfy an increasingly demanding semiconductor market. High-integration in a semiconductor device can be realized by simply reducing the design rule of the semiconductor device and by vertically stacking metal interconnections with interlayer insulating layers between them. High-speed in a semiconductor device can be realized by using an interlayer insulating layer having a low dielectric constant and metal interconnections having a low resistance based on reduction of the design rule of the semiconductor device.
However, after deposition of the interlayer insulating layer, the desired high-speed of the semiconductor device still may not be realized if the interlayer insulating layer is damaged by a subsequent process step. For example, in the case that the interlayer insulating layer and a photoresist pattern are sequentially formed on a semiconductor substrate, the subsequent process of removing the photoresist pattern may employ a plasma ashing technique which uses process gases of H2 and He or process gases of. H2 and NH3. Such a plasma ashing technique, however, physically attacks the interlayer insulating layer by using plasma ions to transform a porous Si—O bonding layer to an Si—H bonding layer downward to a predetermined depth from a top surface of the interlayer insulating layer. Thus, the Si—H bonding layer forms a dense layer in a portion of the interlayer insulating layer. This is the reason that the Si—H bonding layer easily reacts with oxygen in the air while the semiconductor substrate is exposed out of the plasma ashing apparatus, thereby being transformed into an oxidation layer that is chemically different from the remaining portion of the interlayer insulating layer. As a result, the dense oxidation layer has a dielectric constant different from that of the interlayer insulating layer, thereby resulting in adversely affecting the high-speed of the semiconductor device.
In one approach to these familiar problems, U.S. Pat. No. 6,638,851 to Andy Cowley, et. Al (the '851 patent), which is incorporated herein by reference, discloses a dual hardmask single damascene integration scheme using an organic low k interlayer dielectric (ILD). According to the '851 patent, the scheme includes sequentially stacking an organic low k interlayer dielectric layer and first and second inorganic hardmask layers on a semiconductor substrate. A photoresist pattern is deposited on the second inorganic hardmask layer, and, by using the photoresist pattern as an etching mask, an etching process is performed on the second hardmask layer. The etching process patterns the second hardmask layer in accordance with an etching ratio compared with the first hardmask layer. After performing such etching process, a plasma ashing technique is applied to the photoresist pattern, thereby removing the photoresist pattern from the second hardmask layer.
However, in carrying out the process of the '851 patent, through the plasma ashing technique, the first hardmask layer may be physically attacked by plasma ions. Furthermore, the plasma ions which pass through the first hardmask layer may also physically attack the organic interlayer dielectric layer. Therefore, this scheme may cause an undesirable increase in the dielectric constant of the organic interlayer dielectric layer owing to the plasma ashing technique.